Static VSLI semiconductor storage arrays use a single or dual bitline read scheme. Single bitline circuits allow a high density on the cost of noise immunity and performance. This applies in particular to large storage arrays. Dual bitline circuits which use true and complement bitlines for reading out the storage cells are faster and show a higher noise immunity but need more area on the semiconductor chip. Such circuits include a special read head for sensing the voltage difference on the bitlines and convert it to a single data out signal (U.S. Pat. No. 5,949,723).
Known dual bitline read circuits include a bit select circuit, a read head circuit and additional circuits which are required to compensate signal level differences and to achieve full logical signal levels for one and zero bits to produce a reliable data read out. The bit select circuit selects one of a plurality of bitline pairs of those storage cells which are activated by the same word line for a read operation. The storage cells drive the bitlines to full "zero" signals and weak "one" signals respectively where a weak "one" signal is represented by the supply voltage level VDD reduced by the thereshold voltage of the NFET pass device. A bitline swing control circuitry and additional circuitry in the read head circuit is used to compensate this asymmetry.
The bitline swing control circuitry force the bitlines to an intermediate voltage level to reduce the swing of the bitline signals the storage cell has to drive and thereby speeds up the read cycle. The function of the read head circuit is to sense the voltage level difference between the bitlines and to combine the dual read bitlines to a single bitline which is connected to the data out driver. The read head provides an indirect coupling of the bitlines by two cross-coupled PFET devices. This circuitry serves to develop full `one` and `zero` signals for being fed to the data out driver. However, the operation of the cross-coupled PFET devices burdens the speed at which the bit signals are developed. The operation of a known dual bitline read circuit of this type is explained below in more detail with reference to FIG. 1.